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| wireless power transmitter for 3w applications p9235a - r datasheet ? 2016 integrated device technology, inc 1 may 17, 2016 description the p9235a - r is a 3w, magnetic induction , wireless power transmitter for low power applications . the system - on - chip operates with an input voltage range of 4.5 C 5.5v while integrat ing micro - controller, voltage regulation, over - current protection, full bridge power stage drivers and on - chip simultaneous voltage and current demodulation. the transmitter includes industry - leading 32bit arm? cortex? - m0 processor offering a high level of programmability , while consuming extremely low standby power. t he device features two led outputs with pre - defined user programmable blinking patterns, buzzer and programmable over - current protection supporting wide range of applications . the i 2 c serial communication allows the user to read back information such as v oltage, current, frequency and fault conditions . together with the p9 027lp - r receiver, the p9235a - r is a complete wireless power system solution. the p9235a - r is available in a pb - free, space - saving vf qfn 5 mm x 5 mm, 40 pin package. the product is rated over an operating temperature range of - 4 0oc to +85oc. typical applications ? smart watches ? headsets ? health and fitness monitors ? portable medical applications figure 1 . application diagram features ? v in range: 4.5 - 5.5 v ? supports receiver for up to 3w of power transfer ? 80 % peak efficiency (when coupled with p9027lp receiver) ? integrated power stage drivers ? low standby power ? simultaneous v oltage and c urrent d emodulation ? integrated 32 bit arm? cortex? - m0 processor ? supports i 2 c interface for field programmabi lity ? programmable current limit ? over - c urrent and o ver - t emperature protection ? active low enable pin for electrical on/off ? pre - defined programmable led pattern s ? dedicated r emote t emperature s ensing ? - 4 0oc to +85oc ambient operating t emperature r ange ? vf qfn 5mm x 5mm, 40 pin package v i n i s n s _ h i s n s _ l v i n e n o n o f f s c l p 9 2 3 5 a - r g l _ b r g 1 g h _ b r g 1 g l _ b r g 2 g h _ b r g 2 v s n s r s e n s e d i s c r e t e r , c f i l t e r 2 l e d _ g r n l e d _ r e d l d o 3 3 4 . 5 v - 5 . 5 v s w _ b v i n _ l d o v o _ 5 l d o 3 3 l d o 1 8 s d a i l i m l e d _ p a t r s v d 1 r s v d 2 r e s i s t o r d i v i d e r s l d o 1 8 t s l d o 1 8 i s n s _ o u t i s n s _ i n d i s c r e t e r , c f i l t e r 1 v _ b r i d g e
p9235a - r datasheet ? 2016 integrated device technology, inc 2 may 17, 2016 absolute maximum ratings these absolute maximum ratings are stress ratings only. stresses greater than those listed in table 3, 4 and 5 m ay cause permanent damage to the device. functional operation of the p9235a - r at absolute maximum ratings is not implied. exposure to ab solute maximum rating conditions for extended periods may affect long - term reliability. table 1 . ab solute maximum ratings summary (all voltages are referred to ground.) pins rating units en , vin, sw_ b , vbrg_in, sw_brg1, sw_brg2, isns_h, isns_l, bst_brg1, bst_brg2 , gh_brg1, gh_brg2 - 0.3 to 28 v vo_5, vo_33, vin_ldo, led_grn, led_red, vddio, gpio_a4, gpio_b2, gpio_b3, rsvd1, rsvd2, scl, sda, ilim, led_ pat, ts, buz, gl_brg1, gl_brg2, vsns_in, isns_in, isns_out, vdr v_in - 0.3 to 6 v gnd_s, gnd_brg, vsns_gnd, gnd_b, epgnd + 0.3 v ldo18 - 0.3 to 2 v thermal characteristics table 2 1,2,3 . package thermal characteristics symbol description q fn rating units ja thermal resistance junction to ambient 28.5 ? c/w jc thermal resistance junction to case 21 . 87 ? c/w jb thermal resistance junction to board 1.27 ? c/w t j operating junction temperature - 40 to + 12 5 ? c t a ambient operating temperature - 4 0 to + 85 ? c t stg storage temperature - 55 to +150 ? c t lead lead temperature (soldering, 10s) +300 ? c notes: 1. the maximum power dissipation is p d(max) = (t j(max) - t a ) / ja where t j(max) is 85 c. exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. 2. this thermal rating was calculated on jedec 51 standard 4 - layer board with dimensions 3 x 4.5 in still air conditions. 3. actual thermal resistance is affected by pcb size, solder joint quality, layer count, copper thickn ess, air flow, altitude, and other unlisted variables. table 3 . esd information test model pins ratings units hbm all pins +/ - 2000 v cdm all pins. +/ - 500 v p9235a - r datasheet ? 2016 integrated device technology, inc 3 may 17, 2016 electrical characteristics table 4 . device characteristic s v in = 5 v, vddio = 3.3 v, en = 0v, l p = 6.5 h, c p = 400 nf t a = - 40 ? c to +85 ? c. typical values are at 25c, unless otherwise noted. symbol description conditions/notes min typical max units input supplies and uvlo v in input operating range 4.5 5.0 5.5 v v in_uvlo _fw firmware controlled under - voltage lockout . v in rising 4.3 v i std_by 2 standby mode current periodic ping 1 2 ma i shd shutdown current enb = v in 25 80 a enable - en v oh _enb output logic high 2.0 v v ol _enb output logic low 0. 2 5 v buck converter 1,2 - c out =10 f ; l=4.7 h v out buck output voltage v in >5.5v 5 v i out output current 50 ma n - channel mosfet driver s t ls_on_off low side gate drive rise & fall t ime s c l = 3nf ; 10 C 90%, 90 C 10% 50 150 n s t hs_on_off high side gate drive rise & fall t ime s c l = 3nf ; 10 C 90%, 90 C 10% 1 5 0 300 n s input current sense v sen _ ofst amplifier offset v oltage measured at isns_out pin; isns_h=isns_l 0.6 v isen acc_typ me asured current sense accuracy v r_isen =25mv, i=1.25a 3.5 % analog to digital converter n resolution 12 bit channel number of channels 10 v in,fs full scale input voltage 2.4 v ldo18 1,2 - c out =1f; v out18 output voltage 1.71 1.8 1.89 v v out /v out output voltage accuracy 5 % i out18_max maximum load current 1 0 ma ldo33 1,2 - c out =1f ; v out33 output voltage 3.15 3.3 3.45 v v out /v out output voltage accuracy 5 % i out33_max maximum output current 2 0 ma thermal shutdown t sd thermal shutdown threshold rising 140 c threshold falling 120 c p9235a - r datasheet ? 2016 integrated device technology, inc 4 may 17, 2016 table 5 . device characteristic (continued) v in = 5 v, vddio = 3.3 v, en = 0v, l p = 6.5 h, c p = 400 nf t a = - 4 0 ? c to +85 ? c. typical values are at 25c, unless otherwise noted. symbol description conditions/notes min typical max units clock oscillators f lsosc low speed clock 50 k hz f clock osc clock frequency 6 mhz f center 2 pll vco frequency 120 mhz general purpose inputs/outputs (gpio) v ih input high voltage 0.7*vddio v v il input low voltage 0.3*vddio v i lkg leakage current - 1.0 1 .0 a v oh output logic high i=8ma 2.4 v v ol output logic low i=8ma 0.5 v scl, sda (i 2 c interface) f scl_mstr clock frequency as i 2 c master 400 khz f scl_slv clock frequency as i 2 c slave 400 khz c b capacitive load for each bus line 100 pf c bin scl, sda input capacitance 5.0 pf i lkg leakage current 1.0 1.0 a notes: 1. do not externally load. for internal b iasi ng only. 2. guaranteed by design and not subject to 100% production testing p9235a - r datasheet ? 2016 integrated device technology, inc 5 may 17, 2016 typical performance characteristics figure 2 . typical performance characteristics C 3w figure 3 . typical performance characteristics C 2w figure 4 . typical performance characteristics C 1w 45 50 55 60 65 70 75 80 85 60 120 180 240 300 360 420 480 540 600 efficiency (%) iout (ma) efficiency vs current - 3w vin=5v, vout=5v, tx=p9235a - r, tx coil=760308101103, gap=1.5mm, rx coil=760308102213, rx=p9027lp - r, no air flow, room temperature -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 40 80 120 160 200 240 280 320 360 400 load regulation (%) iout (ma) load regulation vs current - 3w vin=5v, vout=5v, tx=p9235a - r, tx coil=760308101104, gap=1.5mm, rx coil=760308101220, rx=p9027lp - r, no air flow, room temperature 25 30 35 40 45 50 55 60 65 70 75 40 80 120 160 200 240 280 320 360 400 efficiency (%) iout (ma) efficiency vs current - 2w vin=5v, vout=5v, tx=p9235a - r, tx coil=760308101104, gap=1.5mm, rx coil=760308101220, rx=p9027lp - r, no air flow, room temperature -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 40 80 120 160 200 240 280 320 360 400 load regulation (%) iout (ma) load regulation vs current - 2w vin=5v, vout=5v, tx=p9235a - r, tx coil=760308101104, gap=1.5mm, rx coil=760308101220, rx=p9027lp - r, no air flow, room temperature 0 10 20 30 40 50 60 20 40 60 80 100 120 140 160 180 200 efficiency (%) iout (ma) efficiency vs current - 1w vin=5v, vout=5v, tx=p9235a - r, tx coil=wt151512 - 21f2, gap=1.5mm, rx coil=wr121220 - 27m8, rx=p9027lp - r, no air flow, room temperature -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 20 40 60 80 100 120 140 160 180 200 loadregulation (%) iout (ma) load regulation vs current - 1w vin=5v, vout=5v, tx=p9235a - r, tx coil=wt151512 - 21f2, gap=1.5mm, rx coil=wr121220 - 27m8, rx=p9027lp - r, no air flow, room temperature p9235a - r datasheet ? 2016 integrated device technology, inc 6 may 17, 2016 pin configuration figure 5 . qfn - 40 5 mm x 5 mm C top view 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 r s v d 2 v d d i o s d a l e d _ p a t i l i m g p i o _ a 4 t s s c l b u z l e d _ r e d 1 2 3 4 5 6 7 8 9 1 0 s w _ b g n d _ b v o _ 3 3 v i n _ l d o v o _ 1 8 r s v d 1 e n g n d _ s v o _ 5 v i n 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 s w _ b r g 2 b s t _ b r g 2 g h _ b r g 2 g p i o _ b 3 g p i o _ b 2 l e d _ g r n s w _ b r g 1 g l _ b r g 1 g n d _ b r g g l _ b r g 2 i s n s _ h i s n s _ l i s n s _ i n v s n s _ g n d v s n s _ i n v b r g _ i n v i n _ d r v i s n s _ o u t g h _ b r g 1 b s t _ b r g 1 e p ( c e n t e r e x p o s e d p a d ) p9235a - r datasheet ? 2016 integrated device technology, inc 7 may 17, 2016 pin description table 6 . pin descriptions pin(s) name type description 1 en i active low enable pin. when connected to logic high, the device shuts down and consumes less than 25 a of current. when connected to logic low, the device is in normal operation. 2 gnd_s - ground connection. 3 vo_5 o regulated output voltage used for the internal device biasing . connect a 1 f capacitor from this pin to ground. this pin should not be externally loaded. 4 vin i input power supply. connect a 10 f capacitor from this pin t o ground. 5 sw_ b o step - down regulator switch node. connect one of the terminals of a 4.7 h inductor to this pin. 6 gnd_b - ground connection. 7 vo_33 o regulated 3.3 v output voltage used for internal device biasing. connect a 1 f capacitor from this pin to ground. this pin should not be externally loaded. 8 vin_ldo i low dropout input power supply. connect this pin to a 5 v source, either to the output of the 5 v output s tep - down regulator or to the i nput power supply pin, vin. 9 vo_18 o regulated 1.8 v output voltage used for internal device biasing. connect a 1 f capacitor from this pin to ground. this pin should not be externally loaded. 10 rsvd1 i this pin is reserved for internal use only. pull down to ground with an external 47 k resistor. 11 rsvd2 i this pin is reserved for internal use only. pull down to ground with an external 47 k resistor. 12 vddio i input power supply for all gpios. can be connected to a power supply ranging from 1.8 C 5.0 v. 13 scl i clock for i 2 c communication . connect a 5.1 k resistor from this pin to vo_5 14 sda i/o data for i 2 c communication. connect a 5.1 k resistor from this pin to vo_5 15 ilim i programmable over - current limit pin. connect a resistor from this pin to gnd to set the current - limit threshold. to disable the current - limit, connect the pin directly to gnd. for more information, s ee current limit application section. 16 led_pat i programmable led pattern selection. connect the center tap of the resistor divider to this pin. for more information on various led blinking pattern, see led pattern application section. 17 gpio _ a4 i/o general purpose input/output. the gpios power is supplied from the vddio pin. this pin is configured as an output. if it is not used then it may be left flo ating. 18 ts i remote temperature sensing. connect a 10 k ntc via a voltage divider to this pin. 19 buz o buzzer pin output . p9235a - r datasheet ? 2016 integrated device technology, inc 8 may 17, 2016 table 7 . pin descriptions (continued) pin(s) name type description 20 led_red o open drain output. connect a red led to this pin. this pin can sink a maximum current of 25 ma (typical) 21 led_grn o open drain output. connect a green led to this pin. this pin can sink a maximum current of 25 ma (typical) 22 gpio_b2 i/o general purpose input/output. the gpios power is supplied from the vddio pin. this pin is configured as an output. if it is not used then it may be left floating. 23 gpio_b3 i/o general purpose input/output. the gpios power is supplied from the vddio pin. this pin is configured as an o utput. if it is not used then it may be left floating. 24 gh_brg2 o gate driver output for the high - side half bridge 2. 25 bst_brg2 i bootstrap pin for the half b ridge 2. tie an external capacitor from this pin to the sw_brg2 to generate a drive voltage, which is higher than the input voltage. 26 sw_brg2 o switch node for half bridge 2. 27 gl_brg2 o gate driver output for the low - side half bridge 2. 28 gnd_brg - ground return connection for half bridge 1 and half bridge 2 external fets and associated components. 29 gl_brg1 o gate driver output for the low - side half bridge 1. 30 sw_brg1 o switch node for half bridge 1. 31 bst_brg1 i bootstrap pin for half b ridge 1. tie an external capacitor from this pin to the sw_brg1 to generate a drive voltage higher than the input voltage. 32 gh_brg1 o gate driver output for the high - side half bridge 1. 33 vin_drv i input power supply for the internal gate drivers. connect a 10 f capacitor from this pin to ground. 34 vbrg_in i bridge v oltage input voltage sense. 3 5 vsns_gnd - ground connection for voltage sense signals. 36 vsns_in i voltage modulation signal input. 37 isns_in i current modulation signal input. isns_out is fed into this pin after external conditioning 38 isns_out o differential ( isns_h - isns_l ) c urrent s ense buffered output . 39 isns_l i input c urrent s ense n egative i nput 40 isns_h i input c urrent s ense p ositive i nput epgnd - expose pad. thermal pad for heat sinking purposes. connect epgnd to gnd plane. p9235a - r datasheet ? 2016 integrated device technology, inc 9 may 17, 2016 figure 6 . p9235a - r block diagram v s n s _ g n d v s n s _ i n v i n _ l d o g n d _ s g p i o _ a 4 i s n s _ o u t v b r g _ i n s w _ b v o _ 5 g n d _ b l d o 3 3 l d o 1 8 s c l s d a r s v d 1 r s v d 2 p r e - r e g c u r r e n t s e n s e a m p l i f i e r r e f e r e n c e h i g h s i d e d r i v e r 1 h a l f / f u l l b r i d g e p w m c o n t r o l l e r d e m o d u l a t i o n ( v s e n s e ) 1 2 - b i t a d c 3 2 - b i t a r m m 0 p r o c e s s o r 1 2 0 m h z p l l l e d d r i v e r b u z d r i v e r 6 m h z o s c l d o 3 . 3 v l o w s i d e d r i v e r 1 b s t _ b r g 1 g h _ b r g 1 s w _ b r g 1 g l _ b r g 1 b s t _ b r g 2 g h _ b r g 2 s w _ b r g 2 v i n _ d r v g n d _ b r g i s n s _ i n b u c k c o n t r o l l e r 3 2 k b o t p 4 k b s r a m i 2 c h i g h s i d e d r i v e r 2 l o w s i d e d r i v e r 2 l d o 1 . 8 v v i n v d d i o i / o m o d u l e g l _ b r g 2 l e d _ g r n l e d _ r e d b u z g p i o _ b 2 g p i o _ b 3 i l i m t s l e d _ p a t d e m o d u l a t i o n ( i s e n s e ) i s n s _ l i s n s _ h m u x e n b r i d g e v o l t a g e s e n s e p9235a - r datasheet ? 2016 integrated device technology, inc 10 may 17, 2016 theory of operation general system architecture a wireless power transfer system has two sub - systems: the w ireless power transmitter ( tx ) and the wireless power receiver ( rx ). the t ransmitter makes power available through a full bridge/half bridge driven lc resonant tank . it transmits power through the generation of an ac magnetic field . once the receiver coil is placed near the magnetic field, the field w ill induce an ac current through the receiving coil where it is converted into a dc current. high level control scheme w ireless power system s adopt a set of pre - defined in - band communication commands as the close loop control strategy. t he amount of power transferred is controlled by the receiver . the receiver sends out c ontrol e rror p ackets (cep) to the transmitter to increase power, decrease power, or maintain the power level. t he transmitter responds by adjust ing the switching frequency and/or duty ratio . the receiver requests more power by send ing out a cep, which includes a positive numerical value. the communication is digital . t he communication 1s and 0s ride on top of the power link that exists between the two coils. wireless power communication when the transmitter is not transferring power to the receiver , it is in the low power standby mode . while in this mode , in order to detect a receiver, the transmitter sends out periodic analog and digital pings . analog pings are very short ac detection p ulses . these short pulses do not transmit enough energy to wake up the receiver , only to detect its presence . digital pings , on the other hand, do transmit enough power to enable the receiver to wake up and begin communication. the transmitter uses d igital pings to listen for a response from a receiver . a fter the transmitter detects a receiver , it may extend the digital ping. this causes the system to proceed to the i dentification and c onfiguration phase. once the receiver is detected and powered up , it will send out communications packets to handshake with the transmitter . the first communication packet the receiver sends out is the signal strength packet, followed by identification packets and configuration packet s . once the handshake process is done , t he receiver will send out periodic control error packets and received power packets to adjust the power. if the receiver needs to stop the power transfer, it will send out an e nd of p ower transfer (ept) communication packet. the transmitter stop s transmit ting power immediately, and start s pre - defined routines according to the information decoded from the ept packet. system fault protection the w ireless power transfer system implements system level protection . these include over voltage, under voltage, ove r current, and over temperature protection . on the transmitter side, whenever a fault condition is detected, it shuts down the whole system immediately and protects itself. i f the receiver detects a fault condition, it will send the end of power transfer packets to shut down the system. the transmitter will continue to transmit power from the time of the receiver fault detection to the reception of the end of power transfer p acket. over voltage protection: if the transmitter v in is greater than 5.5 v , and the system is not in the power transfer mode , then the transmitter will shut down until the v in is in the range of 4.5 v to 5.5 v . if the system is already in the power transfer mode, then the transmitter takes no action. under voltage protection: if the t ransmitter v in is less than 4.5 v, the transmitter will shut down for five minutes, or until the v in is cycled. off/on. over current protection: the transmitter uses a 20 m sense resistor (r sense , r6 ) to monitor the current. if the transmitter detects a c urrent greater than the programmed current limit, it will shut down for five minutes, or until v in is cycled off/on. over temperature protection: if the ts pin (pin 18) voltage falls below 600 mv (typical) then the transmitter will shut down. it will resta rt once the ts voltage rises above 800 mv (200 mv hysteresis) . p9235a - r datasheet ? 2016 integrated device technology, inc 11 may 17, 2016 applications information ldos there are three internal ldos , which supply the p9235a - r internal voltage rails . do not externally load any of the ldos . vo_5 is the output of a high voltage ldo , which serves as the pre - regulator . vo_5 initially supplies the input voltage to the other two ldos until the buck regulator output voltage powers up. the other two ldos , vo_33 and vo_18, have output voltage s of 3.3 v and 1.8 v, respectively. t he analog circuitry is power by the 3.3 v ldo. t he digital circuitry is powered by the 1.8 v ldo . ldo input and output capacitors for proper load voltage regulation and operational stability, low esr ceramic capacitors are required on the input and output of each ldo. a 10 f low esr ceramic cap is recommended for both the input (c19) and output (c14, c27, c29) capacitor s. the capacitor s connection to the ground pin should be as short as possible for optimal device performance. buck regulator the b uck regulator is the power supply for the 3.3 v and 1.8 v ldos, and thus for all the internal analog and digital circuitry , excluding the pre - regulator only. do not externally load any of the ldos . the current sourcing capability of this internal buck regu lator is 5 0 ma maximum . the t wo half bridge gate driver circuits are directly power by the buck regulator. the p9235a - r buck regulator operates in hysteretic pulse mode to set the output voltage and will regulate the output voltage at 5 v (typical) when v in is greater than 5.5 vdc. for operation with vin less than 5.5 v , the buck output will decrease below 5 v . w hen the vin is less than 5 v , the regulator will switch to a linear mode that is similar to a ldo. the input (c18, c19) and output (c20, c21) cap acitors must be connected directly between each power rail pins and power gnd pin (and placed as close as possible to the respective ic pins ) . the output capacitors should be selected based on the typical reference schematic to guarantee control loop stabi lity. a 10 f low esr ceramic cap is recommended for both the bulk input (c19) and bulk output (c21) capacitor . the buck regulator output voltage is connected to the vin_ldo pin; therefore, the connection from the buck output to the vin_ldo pin should be made as wide and short as possible to minimize output voltage errors. buck inductor selection a 4.7 h inductor (l1) is used for the p9235a - r buck regulator . select the inductor saturat ion current rating to exceed the v alue of peak inductor current (during normal operation and start up). the inductor included in the bill of materials is recommended . keep the inductor dcr to a minimum to improve the efficiency of the regulator. decoupling capacitors as with any high - perf ormance mixed - signal ic, p9235a - r must be isolated from the system power supply noise. a decoupling capacitor of 0.1 f should be connected between each power supply pin (includes vin, the buck regulator , ldos , vbrg_in, v_bridge : c18, c20, c28 , c9, c12, c31 ) and the pcb ground plane . it must be placed as close as possible to these pins. t he decoupling capacitor must be mounted on the component side of the pcb. note: t he vo_33 does not need this decoupling capacitor if the user follows the idt recommended, optimized layout. full bridge input capacitor at least one 10 f capacitor (c19) must be placed at the vin pin . at least three 10 f capacitors (c10, c11, c30) must be placed across the full bridge voltage source (the v_bridge node in the schematic) to mi nimize voltage ripple and voltage drop due to the large current requirements. the full - bridge is used to convert dc voltage to ac voltage for power transfer. these 10 f capacitors must be placed as close as possible to the respective pins. note: if the ha lf bridge fets are not physically close together then two 10 f capacitors per half bridge are needed. follow the idt optimized layout in order to minimize these capacitors p9235a - r datasheet ? 2016 integrated device technology, inc 12 may 17, 2016 enable function ( en pin) when voltage on the en pin is greater than 2.5 v , the p9235a - r shuts down the buck regulator . it goes onto shut d own mode , which disables all the analog and digital modules. current consumption in shut d own mode is less than 25 a. when en is less than 1.0 v, the p9 235a - r is fully functional, and all the blocks are enabled. figure 7 shows en thresholds. figure 7 . en pin threshold when en is less than 1.0 v and a receiver is not yet detected, the p9235a - r is in the low power standby mode . t he p9235a - r periodically comes out of standby mode to generate digital and analog pings to detect the presence of a receiver . b etween these pings, the p 9235 a - r continues in the standby mode to maintain low power consumption. input current sense the p9235a - r monitors its input current by using an external sense resistor (r6) , in series with the input voltage rail of the full b ridge lc tank driver circuit (q2, q3) . the voltage across the sense resistor is fed in to the isns_h and isns_l pin via an rc filter (r4,r5,c2) . the differential signal of isns_h and isns_l is processed by the internal adc and associated firmware. the c urr ent sense resistor is sensitive to noise, as well as to circuit board conditions. on the layout of pcb, it is necessary to use kelvin sensing when routing the isns_h and isns_l connections. incorrect current reporting may also occur when a re - worked board has residue (e.g. flux) around the sense resistor. more details are available in the p9235a - r layout guide, an936 . for 2w/3w applications, use a 20m ? sense resistor (r6) . f or 1w applications us e a 50 m? sense resistor . adjust the resistor divider (r27, r31) value on the led_pat pin according to the sense resistor used. communication and modulation t he wireless power system uses an in - band communication, such that the current and voltage on the transmitters power coil assume two states, namely a hi state and a lo state. for a valid state , the amplitude is constant , within a certain variation , for at least t s ms. if the wireles s power receiver is properly aligned to the transmitters power coil, and for all appropriate loads, at least one of the following two conditions shall apply, as shown in figure 8 . d ifference of the amplitude of the transmitter current in the hi and lo state : 15 ma. d ifference of the amplitude of the transmitter voltage in the hi and lo state : 200 mv. the minimum hold time for a valid hi or lo state: 0.15 ms figure 8 . modulation t he receiver uses a 2 khz, differential , bi - phase encoding scheme to modulate data bits onto the power signal. a logic one bit is encoded time v _ en ( v ) v en _ l shutdown mode normal operating mode v en _ h 1 . 0 v 2 . 5 v normal operating mode modulation depth hi state lo state lo state hi state t s t s t s t s p9235a - r datasheet ? 2016 integrated device technology, inc 13 may 17, 2016 using two narrow transitions . a l ogic zero bit is encoded using two wider transitions as shown in figure 9 . figure 9 . bit encoding scheme. each byte in the communication packet comprises 11 bits in an asynchronous serial format. the start bit is always lo . this is followed by 8 bit s of data. the final two bits are parity and stop, as shown in figure 10 . figure 10 . byte encoding scheme. the wireless power receiver communicates with the wireless power transmitter via communication packets. each communica tion packet has the following structure: figure 11 . communication packet structure preamble header message checksum led pattern selection a green led and a red led indicate status. the led patterns d epend on the selected led mode . the voltage applied through resistor divider to the led_pat pin selects the desired led mode . table 8 shows the available selections. note that the l ed pin selection is combined with the input current sense resistor . pulling the led_pat pin to gnd via a 47 k resistor will set the led pattern to the default mode 1. t clk one zero one zero one one zero zero s t a r t s t o p p a r i t y b 0 1 2 3 4 5 6 7 b b b b b b b p9235a - r datasheet ? 2016 integrated device technology, inc 14 may 17, 2016 table 8 . leds indication table pattern current sense resis tor option number voltage on led_pa t pin[v] resistor divider values (input voltage: ldo18) led #/color operational status r top [r27] r bottom [r31] standby transfer complete fault 20 m? 1 pull down <0.037 v np 47 k ,1% led1 - green off on off off led2 - red off off off blink 4 hz 20 m? 2 0.11 v 715 k,1% 47 k ,1% led1 - green on off off off led2 - red on off off blink 4 hz 20 m? 3 0.18 v 422 k,1% 47 k ,1% led1 - green off blink 1 hz on blink 4hz led2 - red - - - - 20 m? 4 0.26 v 280 k,1% 47 k ,1% led1 - green off on off blink 4 hz led2 - red - - - - 20 m? 5 0.33 v 210 k,1% 47 k ,1% led1 - green on blink 1hz on off led2 - red on off off blink 4 hz 20 m? 6 0.41 v 160 k,1% 47 k ,1% led1 - green off off on off led2 - red off on off blink 4 hz 50 m? 7 0.63 v 86.6 k,1% 47 k ,1% led1 - green off on off off led2 - red off off off blink 4 hz 50 m? 8 0.71 v 71.5 k,1% 47 k ,1% led1 - green on off off off led2 - red on off off blink 4 hz 50 m? 9 0.78 v 61. k,1% 47 k ,1% led1 - green off blink 1 hz on blink 4 hz led2 - red - - - - 50 m? 10 0.86 v 51.1 k,1% 47 k ,1% led1 - green off on off blink 4 hz led2 - red - - - - 50 m? 11 0.93 v 44.2 k,1% 47 k ,1% led1 - green on blink 1hz on off led2 - red on off off blink 4 hz 50 m? 12 1.01 v 36.5 k,1% 47 k ,1% led1 - green off off on off led2 - red off on off blink 4 hz input over current protection input over current protection protect s the transmitter half - bridge and receiver from expos ure to conditions that may cause damage or unexpected behavior from the system. while the p9235a - r is in the power transfer stage, it monitor s the input current, through the voltage across the input current sense resistor. if the input current goes above the programmed threshold, the p92 35a - r will shut down for 5 minutes, and then re - try through digital ping s . if the receiver condition remains the same for 5 more minutes, the p9235a - r will continue the periodic analog ping s only (no digital ping s ) . if t he receiver is removed , or the input power is cycled, the p9235a - r will restart digital ping s immediately. the ilim pin voltage selects the input current limit through a voltage divider connected to ldo18. table 9 shows options for 1, 2, and 3w systems, given minimum expected efficiencies . the default value input current limit is 1.25a . the default value occurs when ilim pin is connected to gnd via a 47 k resistor. p9235a - r datasheet ? 2016 integrated device technology, inc 15 may 17, 2016 table 9 . ilim programmable thres holds max power vout /max iout input current limit threshold voltage on ilim pin resistor divider values (input voltage: ldo18) r top [r26] r bottom [r30] 1w 5 v/200 ma 0.75 a 0.48 v 130 k,1% 47 k,1% 2w 5 v/400 ma 1.25 a 0.78 v np 47 k,1% 3w 5 v/600 ma 2.0 a 1.23 v 22 k,1% 47 k,1% remote temperature sensing and over temperature protection the p9235a - r uses a ntc thermistor connected to the ts pin to monitor the remote temperature during the power transfer phase. connect t he ntc thermistor to a voltage divider as shown in figure 15 . if the voltage on the ts pin decreases below 0.6 v, the transmitter shuts off the power , and will resume the wi reless power transfer once the ts pin voltage rises above 0.8 v. figure 12 . ntc connection v ts = ldo33 r thm , trip ( r thm , trip + r bias ) = 600mv where : ? v ts (v) = trip voltage at the desired trip temperature ? r thm,trip (k ) = resistance of the thermistor at the desired trip temperature given ldo33 = 3.3v and r bias =10k , then r thm,trip = 2.22 k at the trip temperature the basic characteristic of an ntc thermistor is : where: ? t (kelvin) = t he trip temperature . ? r 0 (k ) = t he known resistance at calibration temperature t 0 (kelvin) . ? b (beta, kelvin) = t he material constant . with r bias =10k , r thm =2.2k , and v ts =600mv at a trip temperature t, the desired r 0 and b can be calculated, and the appropriate thermistor chosen. ldo 33 ts r bias r thm ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 t 1 t 1 b exp r r p9235a - r datasheet ? 2016 integrated device technology, inc 16 may 17, 2016 buzzer function the buz pin is able to drive a piezoelectric type transducer without amplification. as shown on the reference schematic, a series current limiting resistor (r20) must be included if a buzzer is used . the buzzer signal is a 2 khz square wave . i t is recommended to use a buzzer with a 2 khz resonant frequency for best results. end of power transfer response the p9235a - r will shut down and stop the power transfer once it receives an end of power transfer (ept) packet. t he p9235a - r will behave different ly based on the reason for the ept request. table 10 shows the dif ferent ept behaviors. table 10 . end of power transfer response ept reason p9235a - r b ehavior end of power transfer: over - current the p9235a - r will shut down the system, keeping the analog ping and digital ping. if the over - current condition is not remove d , the system will enter into a hiccup mode . in hiccup mode the following sequence is repeated while the over current condition exists: the system starts up and applies the receiver voltage to the load, the receiver detects a n over current condition and reports it to the transmitter, the transmitter shuts down. end of power transfer: over - temperature the p9235a - r will shut down the system, keeping the analog ping but muting the digital ping for 5 minutes . if the p9027lp - r is removed within 5 minutes, the p9235a - r will restart the digital ping. after 5 minutes, the p9 23 5a - r will send out one digital ping to check if the fault condition has been removed. end of power transfer: charge complete. the p9235a - r will sh ut down the system, keeping the analog ping but mut ing the digital ping for 5 minutes . if the p9027lp - r is removed within 5 minutes , the p9235a - r will restart the digital ping. after 5 minutes , the p9 23 5a - r will send out one digital ping to check if the battery needs to start char g ing again. end of power transfer: internal fault the p9235a - r will shut down the system, keeping the analog ping and digital ping. p9235a - r datasheet ? 2016 integrated device technology, inc 17 may 17, 2016 transmitter resonant tank capacitors for optimum performance , and to keep the characteristic s of the resonant tank constant , t he resonant frequency and quality factor must not change due to variations in the associated capacitors or inductors. the capacitors of the resonant tank (c15, c17, c23, c25) must be cog/npo type only. cog/npo capacitors h ave no temperature variation, less voltage related de - rating, and better accuracy than other types of capacitors such at the x7r. do not mix capacitor types when populating the resonant capacitors, use cog/npo types on ly. all the resonant capacitors must b e rated for 50v. see the bill of materials for the recommended values. transmitter resonant tank coil s e ach half - bridge output connects to a series - resonance lc tank. the inductor serves as the primary coil of a loosely - coupled transformer ; the secondary is the receiver coil connected to the p9027lp - r. the transmitter coils are mounted on a ferrite base acting as a shield to concentrate the field on the top side of the coil and to reduce emi . the coil assembly can be mounted next to the p9235a - r pcb or on the back of pcb. either a ground plane or grounded metal shielding (preferably copper) can be added beneath the ferrite shield for added reduction in radiated electrical field emissions. the c oil ground plane/shield must be connected to the grou nd plane by a single trace leading back independently to the board input power connector. for optimum performance, t he following coils are recommended for use with the p9235a - r transmitter for 1, 2 and 3 w applications. the recommended coil vendors have been tested and verified to guarantee the ir performance . table 11 . coils recommended with receiver for 1, 2 and 3 w applications output power vendor part number inductance dcr dimension 1w tdk wt151512 - 22f2 - id 6.49 uh 0.17 ? ?15 mm sunlord swa15t15h20c01b 6.30 uh 0.12 ? ?15 mm 2w tdk wt202012 - 15f2 - id 6.20 uh 0.10 ? ?20 mm wurth electronics 760308101104 6.30 uh 0.11 ? ?20 mm sunlord swa20n20h20c01b 6.30 uh 0.15 ? ?20 mm 3w tdk wt303012 - 13f2 - id 6.30 uh 0.12 ? ?30 mm wurth electronics 760308101103 6.50 uh 0.15 ? ?30 mm sunlord swa30n30h20c01b 6.25 uh 0.14 ? ?30 mm pcb layout considerations layout and pcb design have a significant influence on the system performance. the p ower dissipation capabilities of the p9235a - r surface mount packaged power management ic rely heavily on thermally conductive traces and pads to transfer heat away from the package. the regulator or full bridge inverter could show instability , as well as cause emi problems , if the pcb layout is not designed properly. the following general guidelines will be helpful in designing a board layout for low noise and emi, as well as, the lowest thermal resistance: 1. pc board traces with large cross - sectional areas remove more heat. f or optimal results, use large - area pcb patterns with wide copper traces, placed on the component side of the pcb. 2. in cases where maximum heat dissipation is required, use double - sided copper planes connected with multiple vias. 3. thermal vias provide a thermal path from the bridge fets to inner and/or bottom layers of the pcb to remove the heat generated by device power dissipation. for more details, please refer to the application note an 936 , p9235a - r layout guidelines for the layout details. p9235a - r datasheet ? 2016 integrated device technology, inc 18 may 17, 2016 po wer dissipation and thermal requirements the p9235a - r is offered in a qfn - 40 package which has a maximum power dissipation capability of approximately 1.2 w . t he number of thermal vias between the package and the printed circuit board determines t he maximum power dissipation. the maximum power dissipation of the package is limited by the dies specified maximum operating junction temperature, t j(max) , of 12 5 c , the maximum ambient operating temperature, t a , of 85 c,and the package thermal resistance, ja . the junction temperature rises when the heat generated by the devices power dissipation flows through the package thermal resistance. the qfn package offers a typical thermal resistance, junction to ambient ( ja ), of 28.5c/w when the pcb layout guideline and surrounding devices are optimized . the techniques as noted in the pcb layout section must be followed when designing the printed circuit board layout. attention to the placement of the p9235a - r ic and bridge fet packages , in proximity to other heat - ge nerating devices in a given application design , should also be considered. the ambient temperature around the power ic will also have an effect on the thermal limits of an applicat ion. the main factors influencing ja (in the order of decreasing influence) are pcb characteristics, die/package attach thermal pad size (qfn) and thermal vias , and final system hardware construction. board designers should keep in mind that the package thermal metric ja is impacted by the characteristics of the pcb itself upon which the ic is mounted. changing the design or configuration of the pcb changes the overall thermal resistivity and the boards heat - sinking efficiency. the use of integrated circuits in low - profile and fine - pitch surface - mount packages requires special a ttention to power dissipation. many system - dependent issues such as thermal coupling, airflow, added heat sinks, convection surfaces, and the presence of other heat - generating components affect the power - dissi pation limits of a given component. in summary, the three basic approaches for enhancing thermal performance are: 1. improv e the power dissipation capability of the pcb design 2. improv e the thermal coupling of the component to the pcb 3. introduc e airflow into the system first, the maximum power dissipation fo r a given situation should be calculated: p d(max) = (t j(max) - t a )/ ja in which ? p d(max) = maximum power dissipation ? ja = package thermal resistance (c/w) ? t j(max) = maximum device junction temperature (c) ? t a = ambient temperature (c) the maximum recommended operating junction temperature (t j(max) ) for the p9235a - r device is 120 c. the thermal resistance of the 40 - pin qfn package is optimally ja =28.5c/w. operation is specified to a maximum steady - state ambient temperature (t a ) of 85 c. therefore, the maximum recommended power dissipation is: p d(max) = ( 120 c - 8 5 c) / 28.5c/w ? 1.2 watt. thermal protection to allow the maximum load current , and to prevent thermal overload , he heat generated by the p9235a - r solution must be dissipated into the pcb . all the available pins must be soldered to the pcb. gnd pins ( exposed paddle, ep ) and bridge fet gnd pins should be soldered to the pcb ground plane to improve thermal performance , with multiple vias connected to all layers of the pcb. special notes ndg qfn - 40 package assembly note 1: unopened dry packaged parts have a one - year shelf life. note 2: the hic indicator card for newly - opened dry packaged parts should be checked. if there is any moisture content, the parts must be baked for a minimum of 8 h ours at 125?c within 24 hours prior to the assembly reflow process. p9235a - r datasheet ? 2016 integrated device technology, inc 19 may 17, 2016 detailed system diagram table 12 . p9235a - r schematic r28 47k r15 np r24 np ts a4 r29 47k r25 np isns_l isns_h r30 47k ilim r26 np r10 np r31 47k r27 np ldo18 u1 P9235A-R enb 1 gnd_s 2 vo_5 3 vin 4 sw_b 5 gnd_b 6 vo_33 7 vin_ldo 8 vo_18 9 rsvd1 10 rsvd2 11 vddio 12 scl 13 sda 14 ilim 15 led_pat 16 gpioa4 17 ts 18 buz 19 led_red 20 led_grn 21 gpiob2 22 gpiob3 23 gh_brg2 24 bst_brg2 25 sw_brg2 26 gl_brg2 27 gnd_brg 28 gl_brg1 29 sw_brg1 30 bst_brg1 31 gh_brg1 32 vin_drv 33 vbrg_in 34 vsns_gnd 35 vsns_in 36 isns_in 37 isns_out 38 isns_l 39 isns_h 40 epgnd 41 led_pat rsvd1 rsvd2 tit le size docum ent num ber rev dat e: sheet of p9235a - r datasheet ? 2016 integrated device technology, inc 20 may 17, 2016 components selection table 13 . component list item qty reference description pcb footprint mfg part number 1 3 c1,c24,c33 22 nf/50 v 0402 c0402c223k5ractu 2 1 c2 1 uf/10 v 0402 c0402c105m8pactu 3 2 c3,c4 220 pf/50 v 0402 cl05b221kb5nnnc 4 1 c5 5.6 nf/50 v 0402 cl05b562kb5nnnc 5 1 c6 6.8 nf/50 v 0402 cl05b682jb5nnnc 6 5 c9,c12,c13,c18,c31 0.1 uf/25 v 0402 tmk105bj104kv - f 7 1 c8 10 uf/10 v 0402 cl05a106mp5nunc 8 5 c10,c11,c19,c21,c30 10 uf/25 v 0603 cl10a106ma8nrnc 9 4 c7,c14,c27,c29 1 uf/10 v 0402 cl05a105kp5nnnc 10 4 c15,c17,c23,c25 100 nf/50 v 1206 c3216c0g1h104j160aa 11 2 c16,c26 100 nf 0402 c1005x6s1v104k050bb 12 3 c20,c34,c28 0.1 uf/10 v 0402 c0402c104k8ractu 13 4 c22,c32,c35,c36 np 0402 14 1 d1 diode sod523pd cmod3003 15 1 d2 red led 0603 150 060 rs7 500 0 16 1 d3 green led 060 150 060 gs7 500 0 17 1 j1 5 p usb_micro_ab 10104111 - 0001lf 18 1 l1 4.7 uh 0603 cig10w4r7mnc 19 1 l2 transmitter coil 7650308101104 20 1 q1 80 mohm/4.5 v sot23 - 6 fdc654p 21 2 q2,q3 n - channel mosfets dfn 3 mm x 3 mm aon7810 22 1 r1 10 k/%1 402 rcg040210k0fked 23 3 r2,r8,r22 1 k 0402 rc0402fr - 071kl 24 1 r3 220 k 0402 rc0402fr - 07220kl 25 2 r4,r5 10 0402 rt0402dre0710rl 26 1 r6 0.02 0603 wsl0805r0200fea 27 3 r7,r13,r19 100 k 0402 erj - 2gej104x 28 4 r9,r12,r14,r16 12 0402 erj - 2gej120x 29 6 r10,r15,r24.r25,r26,r2 7 np 0402 30 2 r11,r18 0 ohms resistor 0402 rc0402jr - 070rl 31 1 r17 5.1 k 0402 mcr01mrtj512 32 1 r20 10 k 0402 crcw040210k0jned 33 1 r21 100 0402 rc0402jr - 07100rl 34 1 r23 680 0402 rc0402jr - 07680rl 35 4 r28,r29,r30,r31 47 k 0402 erj - 2gej473x 36 1 rt1 thermistor 0603 ert - j1vg103fa 37 1 u1 idtp9235 qfn_5 x 5 mm p9235a - r p9235a - r datasheet ? 2016 integrated device technology, inc 21 may 17, 2016 p a ckage drawing figure 13 . qfn - 40 ndg40 package outline drawing p9235a - r datasheet ? 2016 integrated device technology, inc 22 may 17, 2016 landing pattern drawing figure 14 . qfn - 40 ndg40 landing pattern drawing corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1 - 800 - 345 - 7015 or 408 - 284 - 8200 fax: 408 - 284 - 2775 www.idt.com /go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specificat ions and operating parameters of the described products are determined in an independent state and are not guaranteed to perform th e same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt's products for any particular pur pose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt 's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health o r safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreeme nt by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www .idt.com/go/glossary . ? copyright 2016 integrated device technology, inc. all rights reserved. p9235a - r datasheet ordering information orderable part number package msl rating shipping packaging temperature p9235a - rndgi ndg40 - qfn - 40 5x5x0.40 3 tray - 40 to +85c p9235a - rndgi8 ndg40 - qfn - 40 5x5x0.40 3 tape and reel - 40 to +85c marking diagram 1. idt company code, p9235a - r part number. 2. ndg package type: qfn , i industrial 3. # device stepping, yy last 2 digits of the year , ww work week that the part was assembled , $ assembly location code revision history [insert the revision history entries in reverse chronological order.] revision date description of change may 16, 2016 final may 2, 2016 this is the first preliminary release of this datasheet. . |
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